XGS Family

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39

Table 14. SPI TIMING PARAMETERS

Parameter

Symbol

Min

Typ

Max

Unit

SPI Read Frequency (PLL disabled / PLL

enabled)

3.5 / 6.1

MHz

SPI Write Frequency (PLL disabled / PLL

enabled)

12.5 / 25

MHz

Setup Time

ns

Hold Time

ns

Transfer Delay Time

ns

I/O TIMING

External Clock

duty

20%

80%

50%

Figure 53. External Clock Timing

Table 15. EXTERNAL CLOCK SPECIFICATIONS

Parameter

Name

Min

Typ

Max

Unit

Clock Frequency

EXTCLK

29 (Note 15)

32.4

36 (Note 15)

MHz

Duty Cycle

Duty

45

50

55

%

Jitter

Jitter

–

–

100

ps

Rise Time

–

–

5

ns

Fall Time

–

–

5

ns

15.Any deviation from the typical EXTCLK frequency needs to be compensated by reconfiguring the internal PLL (guidelines available upon

request).

Trigger Input

20%

80%

50%

width

Figure 54. Trigger Input Pulse Timing

Table 16. TRIGGER INPUT PULSE SPECIFICATIONS

Parameter

Symbol

Min

Typ

Max

Unit

Pulse Width

width

100

–

−

ns

Rise Time

–

–

5

ns

Fall Time

–

–

5

ns