25CSM04 datasheet(36/55 Pages) MICROCHIP

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25CSM04

DS20005817D-page 36

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Once

the

Partition

Endpoint Addresses

are

programmed to the desired values, it is recommended

that addresses be protected to prevent unintentional

modification. This is accomplished by executing the

Protect Partition Address Boundary (PPAB) instruction

which will modify the PABP bit in the STATUS register

(bit 3, byte 1).

To execute the PPAB instruction, first a WREN instruction

and then a PRWE instruction must be sent to enable

write sequences (see Section 10.2 “Writing to the

Memory Partition Registers”). This will set the WEL

and PREL bits to a logic ‘1’.

Next, as shown in Figure 10-2, the PPAB (34h)

instruction is clocked in on the SI line, followed by any

24-bit address that ends with CC55h in the Least

Significant 16 bits. Finally, a data byte of 00h or FFh is

sent and the self-timed internal write cycle will begin

once the CS pin is driven high.

Using a data byte of FFh will protect the Partition

Endpoint Addresses from being changed by setting the

PABP bit in the STATUS register to logic ‘1’. Sending a

data byte of 00h will unprotect these addresses by

clearing the PABP bit in the STATUS register to

logic ‘0’.

FIGURE 10-2:

PROTECT PARTITION ADDRESS BOUNDARIES (PPAB) SEQUENCE

Note:

The starting address of each partition is

determined by the endpoint address

boundary

the

partition

(00000h

for

MPR0).

Changing

the

address boundary of an MPR can affect

the assigned write-protection behavior for

individual array locations by reassigning

their associated partition.

TABLE 10-2:

MEMORY PARTITION REGISTER PROTECTION MATRIX

FMPC

PABP

Partition Behavior Bits

Partition Endpoint Address Bits

Writable

Protected

Permanently-Protected

Note:

If the CS pin is deasserted before the end

of the 40-bit sequence, the sequence will

be aborted and no write cycle will take

place.

SCK

234

567

9 10 11 12

High-Impedance

0 0 1 1 01

PPAB Opcode (34h)

XX XX X X

D7 D6 D5 D4 D3 D2 D1 D0

MSb

10 1

833

Note 1:

This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.

Address bits A23-A16 are ignored. Address bits A15-A0 must be set to CC55h.

A data byte of FFh will set the PABP bit, while a data byte of 00h will clear the PABP bit.

Address Bits A23-A0(2)

Data In (00h or FFh(3))

TWC(1)

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