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25CSM04-I/MF 数据表(PDF) 21 Page - Microchip Technology |
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25CSM04-I/MF 数据表(HTML) 21 Page - Microchip Technology |
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21 / 55 page  2019-2022 Microchip Technology Inc. and its subsidiares DS20005817D-page 21 25CSM04 When the device is hardware write-protected, the nonvolatile bits of the STATUS register (WPEN, BP1, BP0, WPM, FMPC, PABP) become read-only and the Write STATUS Register (WRSR), Freeze Memory Protection Configuration (FRZR) and Protect Partition Address Boundaries (PPAB), Write Memory Partition Registers (WMPR) and Lock the Security Register (LOCK) instructions will not be accepted. 6.1.2 BLOCK WRITE-PROTECT BITS The 25CSM04 contains four levels of EEPROM write protection using the Block Protection function. The nonvolatile Block Write-Protect bits (BP1, BP0) are located in bits three and two of the first STATUS register byte and define the region of the EEPROM and Security register that are to be treated as read-only. These values are only valid if the device has been set to Legacy Write Protection mode via the WPM STATUS register bit (byte 1, bit 7). The four levels of array protection are: • Level 0 – No portion of the EEPROM is protected, while the lower 256 bytes of the Security register are read-only. • Level 1 – The upper quarter address range is write-protected meaning the highest order 1 Mbits in the EEPROM are read-only. The lower 256 bytes of the Security register are read-only. • Level 2 – The upper half address range is write-protected meaning the highest order 2 Mbits in the EEPROM are read-only. The lower 256 bytes of the Security register are read-only. • Level 3 – Both the EEPROM and Security register are write-protected meaning all addresses are read-only. The address ranges that are protected for each Block Write Protection level and corresponding STATUS register control bits are shown in Table 6-2. TABLE 6-1: REGISTER BEHAVIOR IN LEGACY WRITE PROTECTION AND ENHANCED WRITE PROTECTION MODES Write Protection Mode WP Pin WPEN Bit STATUS Register Memory Partition Registers Legacy or Enhanced Low 0 Not Protected Not Protected Low 1 Protected Protected High X Not Protected Not Protected Note: When the WPEN bit is a logic ‘1’, it cannot be changed back to a logic ‘0’, as long as the WP pin is asserted (low). TABLE 6-2: BLOCK WRITE-PROTECT BITS Level STATUS Register Byte 0 Bits [3:2] Protected Address Range BP1 BP0 Memory Region 25CSM04 0 00 EEPROM None Security Register 00000h-000FFh 1 01 EEPROM 60000h-7FFFFh Security Register 00000h-000FFh 2 10 EEPROM 40000h-7FFFFh Security Register 00000h-000FFh 3 11 EEPROM 00000h-7FFFFh Security Register 00000h-001FFh Note: The Block Protection mechanism will only function with the WPM bit of the STATUS register (bit 7, byte 1) set to a logic ‘0’, indicating Legacy Write Protection mode. If the WPM is set to logic ‘1’, the device will respond in accordance with the Enhanced Write Protection mode. For more details on the Enhanced Write Protection mode, refer to Section 10.1 “Enhanced Write Protection Mode”. |
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