AD8555

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VSS

8

VOUT

7

VCLAMP

6

VPOS

5

VDD

1

FILT/DIGOUT

2

DIGIN

3

VNEG

4

AD8555

TOP VIEW

(Not to Scale)

Figure 2. 8-Lead SOIC (Not Drawn to Scale)

Table 5. 8-Lead SOIC Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VDD

Positive Supply Voltage.

2

FILT/DIGOUT

Unbuffered Amplifier Output In Series with a Resistor RF. Adding a capacitor between FILT and VDD or VSS

implements a low-pass filtering function. In read mode, this pin functions as a digital output.

3

DIGIN

Digital Input.

4

VNEG

Negative Amplifier Input (Inverting Input).

5

VPOS

Positive Amplifier Input (Noninverting Input).

6

VCLAMP

Set Clamp Voltage at Output.

7

VOUT

Buffered Amplifier Output. Buffered version of the signal at the FILT/DIGOUT pin. In read mode, VOUT is a

buffered digital output.

8

VSS

Negative Supply Voltage.

Rev. B | Page 8 of 29