FXLS8964AF datasheet(76/98 Pages) NXP

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NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

This register sets the minimum number of debounce counts needed to recognize the

SDCD within-threshold condition as true.

A transition from Standby to Active, Active to Standby, or a change in an Auto-WAKE/

SLEEP mode change resets the internal counter.

Bit

Name

SDCD_WT_DBCNT[7:0]

Reset (BT_MODE = GND)

Reset (BT_MODE = VDD)

Access

R/W

Table 106. SDCD_WT_DBCNT register (address 32h) bit allocation

Field

Description

7 to 0

SDCD_WT_

DBCNT[7:0]

The SDCD_WT_DBCNT value defines the minimum number of debounce sample counts required

for the detection of an SDCD_WT condition event. The WT_DBCNTM bit determines the behavior of

the counter when the condition of interest is momentarily not true. The time step for the counter is the

same as the selected ODR period (or effective ODR period in FPM).

Table 107. SDCD_WT_DBCNT register (address 32h) bit description

15.31.7 SDCD_LTHS_LSB register (address 33h)

Sensor Data Change Detection function 12-bit 2's complement lower threshold

least significant byte.

SDCD_LTHS[11:0] must always be set to a lower value than

SDCD_UTHS[11:0] to ensure that the SDCD circuit functions correctly and produces

meaningful results.

The scaling for this register is always the same as the selected FSR sensitivity. See

Section 9 for the sensitivity values corresponding to each of the selectable FSRs.

Bit

Name

SDCD_LTHS[7:0]

Reset (BT_MODE = GND)

Reset (BT_MODE = VDD)

Access

R/W

Table 108. SDCD_LTHS_LSB register (address 33h) bit allocation

Field

Description

7 to 0

SDCD_LTHS[7:0]

LSB of the signed 12-bit 2's complement lower threshold value.

Table 109. SDCD_LTHS_LSB register (address 33h) bit description

15.31.8 SDCD_LTHS_MSB register (address 34h)

Sensor Data Change Detection function 12-bit 2's complement lower threshold most

significant byte (nibble).

SDCD_LTHS[11:0] must always be set to a lower value than

FXLS8964AF

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Product data sheet

Rev. 3.4 — 7 December 2021

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