FS3000 Datasheet

R36DS0009EU0100 Rev.1.00

May 31, 2022

Page 8

5.

Functional Description

5.1

I2C Sensor Interface

The FS3000 includes an I2C digital, two-wire interface with a bidirectional data line (SDA) and a clock line (SCL).

The two lines are open drain and connected to the supply voltage via two pull-up resistors (Rp). The FS3000

operates as a slave device on the I2C bus with support of 100kHz and 400kHz bit rates.

Figure 4. I2C Master-Slave Configuration

The recommended pull-up resistor (Rp) values depend on the system implementation, but a value between

2.2kΩ and 10kΩ can be used.

The capacitive load on both SDA and SCL should be the same; therefore, the signal lengths should be similar to

avoid asymmetry.

5.1.1.

Sensor Slave Address

5.1.2.

I2C Communication

The START condition is used to initiate I2C communication by the master. The sensor transmission is initiated

when the master sends a 0 START bit (S). A HIGH-to-LOW transition on the SDA line while the SCL is HIGH

indicates the beginning of a transmission.

The STOP condition is used to stop I2C communication by the master. The transmission is terminated when the

master sends a 1 STOP bit (P). A LOW-to-HIGH transition on the SDA line while the SCL is HIGH indicates the

end of a transmission.

All transfers consist of 8 bits and a response bit: 0 for Acknowledge (ACK) or 1 for Not Acknowledge (NACK).

After the ACK is received, another data byte can be transferred or the communication can be stopped with a

STOP bit.

The master expects an ACK back from the slave after each byte is transmitted. The slave pulls the SDA low to

indicate that it has received a byte and then it frees the I2C bus again. If the slave does not initiate an ACK then

it will consider it a NACK.

Data on the SDA line is always sampled on the rising edge of the SCL line and must remain stable while SCL is

HIGH to prevent false START or STOP conditions.

START Condi tion

STOP Condition

STOP

SDA

SCL

SDA

SCL

START

Figure 5. START and STOP Condition Waveform

I2C MAIN

MASTER

I2C

SLAVE

SDA

SCL

Rp

Rp

Vdd