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R7FA4M2AB3CFM 数据表(PDF) 79 Page - Renesas Technology Corp |
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R7FA4M2AB3CFM 数据表(HTML) 79 Page - Renesas Technology Corp |
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79 / 92 page  Table 2.50 ETM Conditions: High speed high drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Typ Max Unit Test conditions TCLK clock cycle time tTCLKcyc 40 — — ns Figure 2.70 TCLK clock high pulse width tTCLKH 17 — — ns TCLK clock low pulse width tTCLKL 17 — — ns TCLK clock rise time tTCLKr — — 3 ns TCLK clock fall time tTCLKf — — 3 ns TDATA[3:0] output setup time tTRDS 3.5 — — ns Figure 2.71 TDATA[3:0] output hold time tTRDH 2.5 — — ns TCLK tTCLKH tTCLKcyc tTCLKL tTCLKf tTCLKr Figure 2.70 ETM TCLK timing TDATA[3:0] TCLK tTRDS tTRDS tTRDH tTRDH Figure 2.71 ETM output timing RA4M2 Datasheet 2. Electrical Characteristics R01DS0367EJ0110 Rev.1.10 Jan 27, 2021 Page 79 of 92 |
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