CH, CHA

www.vishay.com

Vishay Sfernice

Revision: 27-Apr-2022

2

Document Number: 53014

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

Note

• Suggested land pattern: according to IPC-7351

Dimension and tolerance of land pattern shall be defined by PCB designer; PCB can be designed according to IPC-7351A

“Generic Requirements for Surface Mount Design and Land Pattern Standard”

PERFORMANCE (CH02016 F TERMINATION)

TOLERANCE VS. OHMIC VALUES

Ohmic range

10

Ω ≤ R < 50 Ω

50

Ω ≤ R ≤ 500 Ω

Tolerance CH02016

5 %

1 % for 50

Ω and 100 Ω, 2 %, 5 %

Tolerance CH0402 and CH0603

2 %, 5 %

1 %, 2 %, 5 %

LAND PATTERN FOR F “FLIP CHIP” TERMINATIONS in millimeters (inches)

CHIP SIZE

02016

0.53 (0.021)

0.44 (0.017)

0.15 (0.006)

0402

1.40 (0.055)

0.65 (0.026)

0.40 (0.016)

0603

1.71 (0.067)

0.90 (0.035)

0.76 (0.030)

LAND PATTERN FOR N AND G WRAPAROUND TERMINATIONS in millimeters (inches)

CHIP SIZE

0402

1.55 (0.061)

0.15 (0.006)

0.73 (0.029)

0603

2.37 (0.093)

0.35 (0.014)

0.98 (0.039)

TEST PROCEDURES AND REQUIREMENTS

AEC-Q200

CLAUSE

TEST

PROCEDURE

GLOBAL

PERFORMANCES

TYPICAL

PERFORMANCES

(25

Ω TO 250 Ω)

3

High temperature exposure

MIL-STD-202 method 108

1000 h at T = 125 °C,

unpowered

± 2 % ± 0.05

Ω

± 0.2 % ± 0.05

Ω

4

Temperature cycling

JESD22 method JA-104

1000 cycles (-55 °C to +155 °C)

± 1.8 % ± 0.05

Ω

± 1.5 % ± 0.05

Ω

7

Biased humidity

MIL-STD-202 method 103

1000 h 85 °C / 85 % RH

10 % of operating power

± 2 % ± 0.05

Ω

± 0.75 % ± 0.05

Ω

G

min.

Z

max.

X

max.

G

min.

Z

max.