N2L datasheet(77/127 Pages) RENESAS

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POEGmGn.SSF bit

(m = 0 to 2, n = A to D)

GPT PWM output pins

Outputs disabled

tPOEGDS

Figure 2.52

Output disable time for POEG in response to the register setting

GPT PWM output pins

Oscillation stop detection

signal (internal signal)

Main clock

Outputs disabled

tPOEGDOS

Figure 2.53

Output disable time for POEG in response to the oscillation stop detection

2.5.5.7

A/D Converter Trigger Timing

Table 2.31

A/D converter trigger timing

Parameter

Symbol

Min.

Max.

Unit*1

Reference figure

A/D converter

A/D converter trigger

input pulse width

ADTRG0#,

ADTRG1#

tTRGW

1.5

—

tPADCcyc

Figure 2.54

Note 1. tPADCcyc: PCLKADC cycle

PCLKADC

tTRGW

ADTRG0#

ADTRG1#

Figure 2.54

A/D converter trigger input timing (ADTRG0#, ADTRG1#)

2.5.5.8

SCI Timing

Conditions: VOH = VCC33 × 0.5, VOL = VCC33 × 0.5, C = 30 pF (except Simple I2C)

RZ/N2L Datasheet

2. Electrical Characteristics

R01DS0397EJ0110 Rev.1.10

Jul 29, 2022

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