RZSLASHG datasheet(43/83 Pages) RENESAS

部件名	RZ/G

功能描述	RZ/G2UL, RZ/A3UL, RZ/Five SMARC Module Board

PDF	83 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

标志

43 / 83 page

RZ Family / RZ/G, RZ/A Series

2. Functional Specifications

R01UH0990EJ0101

Rev.1.01

Page 43 of 83

Jul 28, 2022

2.3

Memory

QSPI flash memory and DDR4 SDRAM are mounted on the RTK9743U11C01000BE as external memories.

Please refer to the following for details.

2.3.1

QSPI Flash Memory

Figure 2.1 shows a block diagram of the Serial Flash Memory Interface.

The QSPI flash memory is controlled by the SPI Multi I/O Bus Controller (SPIBSC) that is with built-in to the

RZ/G2UL. This memory supports both single data rate (SDR) and double data rate (DDR) transfers at 66 MHz and 50

MHz clock frequency.

NOTE

The pull-up resistor on the clock line

“RZ_QSPI0_SPCLK” is optional.

Figure 2.1

Block Diagram of Serial Flash Memory I/F

SPI_PVDD

QSPI0_SSL

QSPI0_SPCLK

QSPI0_IO0

QSPI0_IO1

QSPI0_IO2

QSPI0_IO3

RZ/G2UL, RZ/A3UL, RZ/Five

1.8V

RZ/A3UL SMARC Module Board

QSPI Edition

RZ/G2UL SMARC Module Board

RZ/Five SMARC Module Board

RZ/G 数据表(PDF) 43 Page - Renesas Technology Corp

RZ/G 数据表(HTML) 43 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

数据表下载