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MDIO3

MDIO1

MDIO2

MDIO7

MDIO4

MDIO5

MDIO[x]_MDC

MDIO[x]_MDIO

(input)

MDIO[x]_MDIO

(output)

CPSW2G_MDIO_TIMING_01

Figure 7-22. CPSW3G MDIO Timing Requirements and Switching Characteristics

7.10.5.1.2 CPSW3G RMII Timing

Table 7-22, Table 7-23, Figure 7-23, Table 7-24, Figure 7-24 Table 7-25, and Figure 7-25 present timing

conditions, requirements, and switching characteristics for CPSW3G RMII.

Table 7-22. CPSW3G RMII Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

VDD(1) = 1.8V

0.18

0.54

V/ns

VDD(1) = 3.3V

0.4

1.2

V/ns

OUTPUT CONDITIONS

Output load capacitance

(1)

VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see

POWER column of the Pin Attributes table.

Table 7-23. RMII[x]_REF_CLK Timing Requirements – RMII Mode

see Figure 7-23

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

RMII1

tc(REF_CLK)

Cycle time, RMII[x]_REF_CLK

19.999

20.001

RMII2

tw(REF_CLKH)

Pulse Duration, RMII[x]_REF_CLK High

RMII3

tw(REF_CLKL)

Pulse Duration, RMII[x]_REF_CLK Low

RMII[x]_REF_CLK

RMII2

RMII3

RMII1

Figure 7-23. CPSW3G RMII[x]_REF_CLK Timing Requirements – RMII Mode

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AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

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