AM6422...ALV datasheet(144/244 Pages) TI

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Table 7-52. GPMC and NOR Flash Timing Requirements — Synchronous Mode (continued)

see Figure 7-39, Figure 7-40, and Figure 7-43

NO.

PARAMETER

DESCRIPTION

MODE(5)

MIN

MAX

MIN

MAX

UNIT

GPMC_FCLK =

100 MHz(2)

GPMC_FCLK =

133 MHz(2)

F13 th(clkH-dV)

Hold time, input data

GPMC_AD[n:0](1) valid after output

clock GPMC_CLK high

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

2.29

not_div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

2.29

F21 tsu(waitV-clkH)

Setup time, input wait

GPMC_WAIT[j](3) (4) valid before

output clock GPMC_CLK high

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.81

1.12

not_div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.06

3.5

F22 th(clkH-waitV)

Hold time, input wait

GPMC_WAIT[j](3) (4) valid after

output clock GPMC_CLK high

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

2.29

not_div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

2.9

2.29

(1)

Synchronous Mode supports 16-bit data bus up to 133 MHz and 32-bit data bus up to 100 MHz

(2)

GPMC_FCLK select

•

gpmc_fclk_sel[1:0] = 2b01 to select the 100MHz GPMC_FCLK

•

gpmc_fclk_sel[1:0] = 2b00 to select the 133MHz GPMC_FCLK

(3)

In GPMC_WAIT[j], j is equal to 0 or 1.

(4)

Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General-

Purpose Memory Controller (GPMC) section in the device TRM.

(5)

For div_by_1_mode:

•

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:

–

GPMC_CLK frequency = GPMC_FCLK frequency

For not_div_by_1_mode:

•

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:

–

GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)

For GPMC_FCLK_MUX:

•

CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz

For TIMEPARAGRANULARITY_X1:

•

GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/

WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,

OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,

WRDATAONADMUXBUS)

Table 7-53. GPMC and NOR Flash Switching Characteristics – Synchronous Mode

see Figure 7-39, Figure 7-40, Figure 7-41, Figure 7-42, and Figure 7-43

NO.

(3)

PARAMETER

DESCRIPTION

MODE

(17)

MIN

MAX

MIN

MAX

UNIT

100 MHz

133 MHz

1 / tc(clk)

Period, output clock GPMC_CLK

(16)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

10.00

7.52

tw(clkH)

Typical pulse duration, output clock

GPMC_CLK high

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

0.475P

- 0.3(15)

0.475P

- 0.3(15)

AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

www.ti.com

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