AM6422...ALV datasheet(161/244 Pages) TI

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Table 7-57. GPMC and NAND Flash Switching Characteristics – Asynchronous Mode (continued)

see Figure 7-50, Figure 7-51, Figure 7-52 and Figure 7-53

NO.

PARAMETER

MODE

(4)

MIN

MAX UNIT

GNF8 tw(wenIV-aleIV)

Delay time, output write enable GPMC_WEn

invalid to output address valid and address latch

enable GPMC_ADVn_ALE invalid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

F - 2

F + 2

GNF9 tc(wen)

Cycle time, write

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

GNF10 td(csnV-oenV)

Delay time, output chip select GPMC_CSn[i](2)

valid to output enable GPMC_OEn_REn valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

I - 2

I + 2

GNF13 tw(oenV)

Pulse duration, output enable GPMC_OEn_REn

valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

GNF14 tc(oen)

Cycle time, read

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

GNF15 tw(oenIV-CSn[i]V)

Delay time, output enable GPMC_OEn_REn

invalid to output chip select GPMC_CSn[i](2)

invalid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

M - 2

M + 2

(1)

A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(3)

(2)

In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

(3)

GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

(4)

For div_by_1_mode:

•

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:

–

GPMC_CLK frequency = GPMC_FCLK frequency

For GPMC_FCLK_MUX:

•

CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz

For TIMEPARAGRANULARITY_X1:

•

GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/

WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,

OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,

WRDATAONADMUXBUS)

GPMC_FCLK

GPMC_CSn[i]

GPMC_BE0n_CLE

GPMC_ADCn_ALE

GPMC_OEn_REn

GPMC_WEn

GPMC_AD[15:0]

Command

GNF0

GNF1

GNF2

GNF3

GNF4

GNF5

GNF6

GPMC_12

In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

Figure 7-50. GPMC and NAND Flash — Command Latch Cycle

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AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

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