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XAM2434...ALX 数据表(PDF) 161 Page - Texas Instruments |
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XAM2434...ALX 数据表(HTML) 161 Page - Texas Instruments |
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161 / 280 page  7.10.5.6 FSI Table 7-44, Table 7-45, Figure 7-36, Table 7-46, Figure 7-37, Table 7-47, and Figure 7-38 present timing conditions, requirements, and switching characteristics for FSI. Table 7-44. FSI Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.8 4 V/ns OUTPUT CONDITIONS CL Output load capacitance 1 7 pF Table 7-45. FSI Timing Requirements see Figure 7-36 NO. MIN MAX UNIT FSIR1 tc(RX_CLK) Cycle time, FSI_RXn_CLK 20 ns FSIR2 tw(RX_CLK) Pulse width, FSI_RXn_CLK low or FSI_RXn_CLK high 0.5P - 1 (1) 0.5P + 1 (1) ns FSIR3 tsu(RX_D-RX_CLK) Setup time, FSI_RXn_D[1:0] valid before FSI_RXn_CLK 3 ns FSIR4 th(RX_CLK-RX_D) Hold time, FSI_RXn_D[1:0] valid after FSI_RXn_CLK 2.5 ns (1) P = FSI_RXn_CLK period in ns. FSI_RXn_CLK FSIR2 FSIR1 FSIR3 FSI_RXn_D0 FSI_RXn_D1 FSIR4 FSIR2 Figure 7-36. FSI Timing Requirements www.ti.com AM2434, AM2432, AM2431 SPRSP65D – APRIL 2021 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 161 Product Folder Links: AM2434 AM2432 AM2431 |
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