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XAM2434...ALX 数据表(PDF) 165 Page - Texas Instruments |
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XAM2434...ALX 数据表(HTML) 165 Page - Texas Instruments |
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165 / 280 page  Table 7-52. GPMC and NOR Flash Timing Requirements — Synchronous Mode (continued) see Figure 7-39, Figure 7-40, and Figure 7-43 NO. PARAMETER DESCRIPTION MODE(5) MIN MAX MIN MAX UNIT GPMC_FCLK = 100 MHz(2) GPMC_FCLK = 133 MHz(2) F22 th(clkH-waitV) Hold time, input wait GPMC_WAIT[j](3) (4) valid after output clock GPMC_CLK high div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 2.29 2.29 ns not_div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 2.29 2.29 ns (1) Synchronous Mode supports 16-bit data bus up to 133 MHz and 32-bit data bus up to 100 MHz (2) GPMC_FCLK select • gpmc_fclk_sel[1:0] = 2b01 to select the 100MHz GPMC_FCLK • gpmc_fclk_sel[1:0] = 2b00 to select the 133MHz GPMC_FCLK (3) In GPMC_WAIT[j], j is equal to 0 or 1. (4) Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General- Purpose Memory Controller (GPMC) section in the device TRM. (5) For div_by_1_mode: • GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h: – GPMC_CLK frequency = GPMC_FCLK frequency For not_div_by_1_mode: • GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h: – GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4) For GPMC_FCLK_MUX: • CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz For TIMEPARAGRANULARITY_X1: • GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/ WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS) Table 7-53. GPMC and NOR Flash Switching Characteristics – Synchronous Mode see Figure 7-39, Figure 7-40, Figure 7-41, Figure 7-42, and Figure 7-43 NO. (3) PARAMETER DESCRIPTION MODE (17) MIN MAX MIN MAX UNIT 100 MHz 133 MHz F0 1 / tc(clk) Period, output clock GPMC_CLK (16) div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 10.00 7.52 ns F1 tw(clkH) Typical pulse duration, output clock GPMC_CLK high div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 0.475P - 0.3(15) 0.475P - 0.3(15) ns F1 tw(clkL) Typical pulse duration, output clock GPMC_CLK low div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 0.475P - 0.3(15) 0.475P - 0.3(15) ns F2 td(clkH-csnV) Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[i] transition (14) div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1; no extra_delay F - 2.2 (6) F + 3.75 F - 2.2 (6) F + 3.75 ns F3 td(clkH-CSn[i]V) Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[i] invalid (14) div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1; no extra_delay E - 2.2 (5) E + 3.18 E - 2.2 (5) E + 4.5 ns F4 td(aV-clk) Delay time, output address GPMC_A[27:1] valid to output clock GPMC_CLK first edge div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 B - 2.3 (3) B + 4.5 B - 2.3 (3) B + 4.5 ns www.ti.com AM2434, AM2432, AM2431 SPRSP65D – APRIL 2021 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 165 Product Folder Links: AM2434 AM2432 AM2431 |
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