SAF7741HV datasheet(39/83 Pages) NXP

39 / 83 page

SAF7741_5

Objective data sheet

Rev. 05 — 09 May 2008

39 of 83

NXP Semiconductors

SAF7741HV

Dual IF car radio and audio DSP (N1F)

7.4.1.1

General description of the SPDIF inputs

The design fulfils the requirements of the IEC60958 Digital Audio Interface specification

(see Ref. 6) except for the input voltage, which is required to have a digital level. The

interface is compliant with the electrical limitations of the pins (see Table 23).

There are two SPDIF independent input pins with their own SPDIF receivers. This means

that two SPDIF signals can be processed in parallel.

The SPDIF receiver is not fitted with an analog PLL. The incoming SPDIF stream is

sampled at a high frequency in the digital domain. From the SPDIF signal a 3-wire (I2S-

like) serial bus is made consisting of word-select, data and bitclock lines. The Fs

frequency depends solely on the accuracy of the SPDIF signal input.

This design does not handle the user data bits of the SPDIF stream. The audio field of up

to 24 bits is available at its output. The audio bits are always decoded regardless of any

status bits; e.g. copy-protected, professional mode or data mode. However, a subset of

the channel status bits is decoded and made available to the ADSP and the SDSP. In

addition, the 'validity' bit is available. This means that the ADSP can prevent non-PCM

audio or data being processed as audio. See the relevant tables in Ref. 3 for the exact

channel status bits supported. The supported bits are extracted from the left channel only.

SPDIF format: The SPDIF format was conceived to transport 2-channel PCM audio for

distances of up to several hundred metres over a 3-wire balanced line. Alternatively the

signal could be carried for shorter distances over a 2-wire pair.

The SPDIF format can be partitioned into two main layers:

• The abstract model of frames and blocks

• The channel modulation

SPDIF channel modulation: The digital signal is coded using Bi-phase Mark Coding

(BMC), which is a type of phase modulation. In this scheme a logical 1 in the data

corresponds to two zero crossings in the coded signal and a logical 0 to one zero

crossing.

Since a logic 1 implies two transitions in the BMC signal, a clock at twice the bit rate

assumes the use of all rising signal edges.

SPDIF sample rates: The IEC60958 specification allows the use of sample rates from

22.05 kHz to 192 kHz. The SAF7741HV is designed to support a very wide range of

sample rates, but there are restrictions with respect to the processing power of the SDSP

Fig 29. Bi-phase mark coding

Clock

Data

BMC

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