DVR21 datasheet(206/416 Pages) MICROCHIP

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PIC24FJ256GA705 FAMILY

DS30010118D-page 206

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SPIxCON1H: SPIx CONTROL REGISTER 1 HIGH

R/W-0

AUDEN(1)

SPISGNEXT

IGNROV

IGNTUR

AUDMONO(2) URDTEN(3) AUDMOD1(4) AUDMOD0(4)

bit 15

bit 8

R/W-0

FRMEN

FRMSYNC

FRMPOL

MSSEN

FRMSYPW

FRMCNT2

FRMCNT1

FRMCNT0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

AUDEN: Audio Codec Support Enable bit(1)

1 = Audio protocol is enabled; MSTEN controls the direction of both the SCKx and frame (a.k.a. LRC),

and this module functions as if FRMEN = 1, FRMSYNC = MSTEN, FRMCNT<2:0> = 001 and

SMP = 0, regardless of their actual values

0 = Audio protocol is disabled

bit 14

SPISGNEXT: SPIx Sign-Extend RX FIFO Read Data Enable bit

1 = Data from RX FIFO is sign-extended

0 = Data from RX FIFO is not sign-extended

bit 13

IGNROV: Ignore Receive Overflow bit

1 = A Receive Overflow (ROV) is NOT a critical error; during ROV, data in the FIFO is not overwritten

by the receive data

0 = A ROV is a critical error that stops SPI operation

bit 12

IGNTUR: Ignore Transmit Underrun bit

1 = A Transmit Underrun (TUR) is NOT a critical error and data indicated by URDTEN is transmitted

until the SPIxTXB is not empty

0 = A TUR is a critical error that stops SPI operation

bit 11

AUDMONO: Audio Data Format Transmit bit(2)

1 = Audio data is mono (i.e., each data word is transmitted on both left and right channels)

0 = Audio data is stereo

bit 10

URDTEN: Transmit Underrun Data Enable bit(3)

1 = Transmits data out of SPIxURDTL/H register during Transmit Underrun conditions

0 = Transmits the last received data during Transmit Underrun conditions

bit 9-8

AUDMOD<1:0>: Audio Protocol Mode Selection bits(4)

11 = PCM/DSP mode

10 = Right Justified mode: This module functions as if SPIFE = 1, regardless of its actual value

01 = Left Justified mode: This module functions as if SPIFE = 1, regardless of its actual value

00 = I2S mode: This module functions as if SPIFE = 0, regardless of its actual value

bit 7

FRMEN: Framed SPIx Support bit

1 = Framed SPIx support is enabled (SSx pin is used as the FSYNC input/output)

0 = Framed SPIx support is disabled

Note 1:

AUDEN can only be written when the SPIEN bit = 0.

AUDMONO can only be written when the SPIEN bit = 0 and is only valid for AUDEN = 1.

URDTEN is only valid when IGNTUR = 1.

AUDMOD<1:0> bits can only be written when the SPIEN bit = 0 and are only valid when AUDEN = 1.

When NOT in PCM/DSP mode, this module functions as if FRMSYPW = 1, regardless of its actual value.

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