DVR21 datasheet(100/416 Pages) MICROCHIP

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PIC24FJ256GA705 FAMILY

DS30010118D-page 100

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OSCCON: OSCILLATOR CONTROL REGISTER(1)

U-0

R-x(2)

U-0

R/W-x(2)

—

COSC2

COSC1

COSC0

—

NOSC2

NOSC1

NOSC0

bit 15

bit 8

R/W-0

R-0(4)

U-0

R/CO-0

R/W-0

CLKLOCK

IOLOCK(3)

LOCK

—

POSCEN

SOSCEN

OSWEN

bit 7

bit 0

Legend:

CO = Clearable Only bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

COSC<2:0>: Current Oscillator Selection bits(2)

111 = Oscillator with Frequency Divider (OSCFDIV)

110 = Reserved

101 = Low-Power RC Oscillator (LPRC)

100 = Secondary Oscillator (SOSC)

011 = Primary Oscillator with PLL module (XTPLL, ECPLL)

010 = Primary Oscillator (XT, HS, EC)

001 = Fast RC Oscillator with PLL module (FRCPLL)

000 = Fast RC Oscillator (FRC)

bit 11

Unimplemented: Read as ‘0’

bit 10-8

NOSC<2:0>: New Oscillator Selection bits(2)

111 = Oscillator with Frequency Divider (OSCFDIV)

110 = Reserved

101 = Low-Power RC Oscillator (LPRC)

100 = Secondary Oscillator (SOSC)

011 = Primary Oscillator with PLL module (XTPLL, ECPLL)

010 = Primary Oscillator (XT, HS, EC)

001 = Fast RC Oscillator with PLL module (FRCPLL)

000 = Fast RC Oscillator (FRC)

bit 7

CLKLOCK: Clock Selection Lock Enable bit

If FSCM is Enabled (FCKSM<1:0> = 00):

1 = Clock and PLL selections are locked

0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit

If FSCM is Disabled (FCKSM<1:0> = 1x):

Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.

bit 6

IOLOCK: I/O Lock Enable bit(3)

1 = I/O lock is active

0 = I/O lock is not active

bit 5

LOCK: PLL Lock Status bit(4)

1 = PLL module is in lock or PLL module start-up timer is satisfied

0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled

Note 1:

OSCCON is protected by a write lock to prevent inadvertent clock switches. See Section 9.4 “Clock

Switching Operation” for more information.

Reset values for these bits are determined by the FNOSCx Configuration bits.

The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In

addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared.

This bit also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.

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