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DVR21 数据表(PDF) 219 Page - Microchip Technology |
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DVR21 数据表(HTML) 219 Page - Microchip Technology |
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219 / 416 page  2016-2018 Microchip Technology Inc. DS30010118D-page 219 PIC24FJ256GA705 FAMILY FIGURE 17-4: SPIx MASTER, FRAME MASTER CONNECTION DIAGRAM PIC24FJ256GA705 Serial Clock SCKx Frame Sync Pulse(1,2) SDIx SDOx Processor 2 SSx SCKx (SPIx Master, Frame Master) Serial Receive Buffer (SPIxRXB)(3) Shift Register (SPIxRXSR) Shift Register (SPIxTXSR) Serial Transmit Buffer (SPIxTXB)(3) (SPIxBUF) SPI Buffer Serial Receive Buffer (SPIxTXB)(3) Shift Register (SPIxRXSR) Shift Register (SPIxTXSR) Serial Transmit Buffer (SPIxTXB)(3) (SPIxBUF) SPI Buffer (SPIx Slave, Frame Slave) SSx(1) SDOx SDIx MSb LSb MSb LSb MSb LSb MSb LSb Note 1: In Framed SPI modes, the SSx pin is used to transmit/receive the Frame Synchronization pulse. 2: Framed SPI modes require the use of all four pins (i.e., using the SSx pin is not optional). 3: The SPIxTXB and SPIxRXB registers are memory-mapped to the SPIxBUF register. |
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