DVR21 datasheet(273/416 Pages) MICROCHIP

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DS30010118D-page 273

PIC24FJ256GA705 FAMILY

22.1.3

DATA SHIFT DIRECTION

The LENDIAN bit (CRCCON1<3>) is used to control

the shift direction. By default, the CRC will shift data

through the engine, MSb first. Setting LENDIAN (= 1)

causes the CRC to shift data, LSb first. This setting

allows better integration with various communication

schemes and removes the overhead of reversing the

bit order in software. Note that this only changes the

direction the data is shifted into the engine. The result

of the CRC calculation will still be a normal CRC result,

not a reverse CRC result.

22.1.4

INTERRUPT OPERATION

The module generates an interrupt that is configurable

by the user for either of two conditions.

If CRCISEL is ‘0’, an interrupt is generated when the

VWORD<4:0> bits make a transition from a value of ‘1’

to ‘0’. If CRCISEL is ‘1’, an interrupt will be generated

after the CRC operation finishes and the module sets

the CRCGO bit to ‘0’. Manually setting CRCGO to ‘0’

will not generate an interrupt. Note that when an

interrupt occurs, the CRC calculation would not yet be

complete. The module will still need (PLENx + 1)/2

clock cycles after the interrupt is generated until the

CRC calculation is finished.

22.1.5

TYPICAL OPERATION

To use the module for a typical CRC calculation:

Set the CRCEN bit to enable the module.

Configure the module for desired operation:

Program the desired polynomial using the

CRCXOR registers and PLEN<4:0> bits.

Configure the data width and shift direction

using the DWIDTH<4:0> and LENDIAN bits.

Set the CRCGO bit to start the calculations.

Set the desired CRC non-direct initial value by

writing to the CRCWDAT registers.

Load all data into the FIFO by writing to the

CRCDAT registers as space becomes available

(the CRCFUL bit must be zero before the next

data loading).

Wait until the data FIFO is empty (CRCMPT bit

is set).

Read the result:

If the data width (DWIDTH<4:0> bits) is more

than the polynomial length (PLEN<4:0> bits):

Wait (DWIDTH<4:0> + 1)/2 instruction cycles

to make sure that shifts from the shift buffer

are finished.

Change the data width to the polynomial

length (DWIDTH<4:0> = PLEN<4:0>).

Write one dummy data word to the CRCDAT

registers.

Wait two instruction cycles to move the data

from the FIFO to the shift buffer and

(PLEN<4:0> + 1)/2 instruction cycles to

shift out the result.

Or, if the data width (DWIDTH<4:0> bits) is less than

the polynomial length (PLEN<4:0> bits):

Clear

the

CRC

Interrupt

Selection

bit

(CRCISEL = 0) to get the interrupt when all

shifts are done. Clear the CRC interrupt flag.

Write dummy data in the CRCDAT registers and

wait until the CRC interrupt flag is set.

Read the final CRC result from the CRCWDAT

registers.

Restore the data width (DWIDTH<4:0> bits) for

further calculations (optional). If the data width

(DWIDTH<4:0> bits) is equal to, or less than, the

polynomial length (PLEN<4:0> bits):

a) Clear the CRC Interrupt Selection bit

(CRCISEL = 0) to get the interrupt when all

shifts are done.

b) Suspend

the

calculation

setting

CRCGO = 0.

Clear the CRC interrupt flag.

d) Write the dummy data with the total data

length equal to the polynomial length in the

CRCDAT registers.

e) Resume

the

calculation

setting

CRCGO = 1.

Wait until the CRC interrupt flag is set.

Read the final CRC result from the

CRCWDAT registers.

There are eight registers used to control programmable

CRC operation:

• CRCCON1

• CRCCON2

• CRCXORL

• CRCXORH

• CRCDATL

• CRCDATH

• CRCWDATL

• CRCWDATH

The CRCCON1 and CRCCON2 registers (Register 22-1

and Register 22-2) control the operation of the module

and configure the various settings.

The

CRCXOR

registers

(Register 22-3

and

in the CRC equation. The CRCDAT and CRCWDAT

registers are each register pairs that serve as buffers

for the double-word input data, and CRC processed

output, respectively.

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