DVR21 datasheet(281/416 Pages) MICROCHIP

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DS30010118D-page 281

PIC24FJ256GA705 FAMILY

bit 2-0

MODE<2:0>: CLCx Mode bits

111 = Cell is a 1-input transparent latch with S and R

110 = Cell is a JK flip-flop with R

101 = Cell is a 2-input D flip-flop with R

100 = Cell is a 1-input D flip-flop with S and R

011 = Cell is an SR latch

010 = Cell is a 4-input AND

001 = Cell is an OR-XOR

000 = Cell is an AND-OR

CLCxCONL: CLCx CONTROL REGISTER (LOW) (CONTINUED)

CLCxCONH: CLCx CONTROL REGISTER (HIGH)

U-0

—

bit 15

bit 8

U-0

R/W-0

—

G4POL

G3POL

G2POL

G1POL

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-4

Unimplemented: Read as ‘0’

bit 3

G4POL: Gate 4 Polarity Control bit

1 = The output of Channel 4 logic is inverted when applied to the logic cell

0 = The output of Channel 4 logic is not inverted

bit 2

G3POL: Gate 3 Polarity Control bit

1 = The output of Channel 3 logic is inverted when applied to the logic cell

0 = The output of Channel 3 logic is not inverted

bit 1

G2POL: Gate 2 Polarity Control bit

1 = The output of Channel 2 logic is inverted when applied to the logic cell

0 = The output of Channel 2 logic is not inverted

bit 0

G1POL: Gate 1 Polarity Control bit

1 = The output of Channel 1 logic is inverted when applied to the logic cell

0 = The output of Channel 1 logic is not inverted

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