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DVR21 数据表(PDF) 165 Page - Microchip Technology |
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DVR21 数据表(HTML) 165 Page - Microchip Technology |
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165 / 416 page ![]() 2016-2018 Microchip Technology Inc. DS30010118D-page 165 PIC24FJ256GA705 FAMILY bit 3 T32: 32-Bit Timer Mode Select bit(3) 1 = Timerx and Timery form a single 32-bit timer 0 = Timerx and Timery act as two 16-bit timers In 32-bit mode, T3CON control bits do not affect 32-bit timer operation. bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timerx Clock Source Select bit(2) 1 = Timer source is selected by TECS<1:0> 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ REGISTER 13-1: TxCON: TIMER2 CONTROL REGISTER(1) (CONTINUED) Note 1: Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. 2: If TCS = 1 and TECS<1:0> = x1, the selected external timer input (TxCK or TyCK) must be configured to an available RPn/RPIn pin. For more information, see Section 11.5 “Peripheral Pin Select (PPS)”. 3: In 32-bit mode, the T3CON control bits do not affect 32-bit timer operation. |
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