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F21 数据表(PDF) 191 Page - Microchip Technology |
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F21 数据表(HTML) 191 Page - Microchip Technology |
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191 / 416 page ![]() 2016-2018 Microchip Technology Inc. DS30010118D-page 191 PIC24FJ256GA705 FAMILY bit 3-0 MOD<3:0>: CCPx Mode Select bits For CCSEL = 1 (Input Capture modes): 1xxx = Reserved 011x = Reserved 0101 = Capture every 16th rising edge 0100 = Capture every 4th rising edge 0011 = Capture every rising and falling edge 0010 = Capture every falling edge 0001 = Capture every rising edge 0000 = Capture every rising and falling edge (Edge Detect mode) For CCSEL = 0 (Output Compare/Timer modes): 1111 = External Input mode: Pulse generator is disabled, source is selected by ICS<2:0> 1110 = Reserved 110x = Reserved 10xx = Reserved 0111 = Variable Frequency Pulse mode 0110 = Center-Aligned Pulse Compare mode, buffered(1) 0101 = Dual Edge Compare mode, buffered 0100 = Dual Edge Compare mode 0011 = 16-Bit/32-Bit Single Edge mode, toggles output on compare match 0010 = 16-Bit/32-Bit Single Edge mode, drives output low on compare match 0001 = 16-Bit/32-Bit Single Edge mode, drives output high on compare match 0000 = 16-Bit/32-Bit Timer mode, output functions are disabled REGISTER 16-1: CCPxCON1L: CCPx CONTROL 1 LOW REGISTERS (CONTINUED) Note 1: Center-Aligned PWM mode is only available on MCCP modules. This feature is disabled on SCCP modules. |
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