F21 datasheet(82/416 Pages) MICROCHIP

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PIC24FJ256GA705 FAMILY

DS30010118D-page 82

 2016-2018 Microchip Technology Inc.

7.1

Special Function Register Reset

States

Most of the Special Function Registers (SFRs) associ-

ated with the PIC24F CPU and peripherals are reset to a

particular value at a device Reset. The SFRs are

grouped by their peripheral or CPU function and their

Reset values are specified in each section of this manual.

The Reset value for each SFR does not depend on the

type of Reset, with the exception of four registers. The

Reset value for the Reset Control register, RCON, will

depend on the type of device Reset. The Reset value

for the Oscillator Control register, OSCCON, will

depend on the type of Reset and the programmed

values of the FNOSC<2:0> bits in the FOSCSEL Flash

Configuration Word (see Table 7-2). The RCFGCAL

and NVMCON registers are only affected by a POR.

7.2

Device Reset Times

The Reset times for various types of device Reset are

summarized in Table 7-3. Note that the Master Reset

Signal, SYSRST, is released after the POR delay time

expires.

The time at which the device actually begins to execute

code will also depend on the system oscillator delays,

which include the Oscillator Start-up Timer (OST) and

the PLL lock time. The OST and PLL lock times occur

in parallel with the applicable SYSRST delay times.

The Fail-Safe Clock Monitor (FSCM) delay determines

the time at which the FSCM begins to monitor the system

clock source after the SYSRST signal is released.

7.3

Brown-out Reset (BOR)

PIC24FJ256GA705 family devices implement a BOR

circuit that provides the user with several configuration

and power-saving options. The BOR is controlled by the

BOREN<1:0> (FPOR<1:0>) Configuration bits.

When BOR is enabled, any drop of VDD below the BOR

threshold results in a device BOR. Threshold levels are

described in Section 32.1 “DC Characteristics”.

7.4

Clock Source Selection at Reset

If clock switching is enabled, the system clock source at

device Reset is chosen, as shown in Table 7-2. If clock

switching is disabled, the system clock source is always

selected according to the Oscillator Configuration bits.

For more information, refer to the “dsPIC33/PIC24

Family Reference Manual”, “Oscillator” (DS39700).

TABLE 7-2:

OSCILLATOR SELECTION vs.

TYPE OF RESET (CLOCK

SWITCHING ENABLED)

Reset Type

Clock Source Determinant

POR

FNOSC<2:0> Configuration bits

(FOSCSEL<2:0>)

BOR

MCLR

COSC<2:0> Control bits

(OSCCON<14:12>)

WDTO

SWR

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