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F21 数据表(PDF) 196 Page - Microchip Technology |
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F21 数据表(HTML) 196 Page - Microchip Technology |
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196 / 416 page ![]() PIC24FJ256GA705 FAMILY DS30010118D-page 196 2016-2018 Microchip Technology Inc. REGISTER 16-5: CCPxCON3L: CCPx CONTROL 3 LOW REGISTERS(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — —DT<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 DT<5:0>: CCPx Dead-Time Select bits(1) 111111 = Inserts 63 dead-time delay periods between complementary output signals 111110 = Inserts 62 dead-time delay periods between complementary output signals . . . 000010 = Inserts 2 dead-time delay periods between complementary output signals 000001 = Inserts 1 dead-time delay period between complementary output signals 000000 = Dead-time logic is disabled Note 1: This register is implemented in the MCCP1 module only. |
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