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F21 数据表(PDF) 205 Page - Microchip Technology |
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F21 数据表(HTML) 205 Page - Microchip Technology |
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205 / 416 page ![]() 2016-2018 Microchip Technology Inc. DS30010118D-page 205 PIC24FJ256GA705 FAMILY bit 8 CKE: SPIx Clock Edge Select bit(1) 1 = Transmit happens on transition from active clock state to Idle clock state 0 = Transmit happens on transition from Idle clock state to active clock state bit 7 SSEN: Slave Select Enable bit (Slave mode)(2) 1 = SSx pin is used by the macro in Slave mode; SSx pin is used as the slave select input 0 = SSx pin is not used by the macro (SSx pin will be controlled by the port I/O) bit 6 CKP: SPIx Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level bit 5 MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode bit 4 DISSDI: Disable SDIx Input Port bit 1 = SDIx pin is not used by the module; pin is controlled by the port function 0 = SDIx pin is controlled by the module bit 3 DISSCK: Disable SCKx Output Port bit 1 = SCKx pin is not used by the module; pin is controlled by the port function 0 = SCKx pin is controlled by the module bit 2 MCLKEN: Master Clock Enable bit(3) 1 = MCLK is used by the BRG(5) 0 = Peripheral Clock is used by the BRG bit 1 SPIFE: Frame Sync Pulse Edge Select bit 1 = Frame Sync pulse (Idle-to-active edge) coincides with the first bit clock 0 = Frame Sync pulse (Idle-to-active edge) precedes the first bit clock bit 0 ENHBUF: Enhanced Buffer Mode Enable bit 1 = Enhanced Buffer mode is enabled 0 = Enhanced Buffer mode is disabled REGISTER 17-1: SPIxCON1L: SPIx CONTROL REGISTER 1 LOW (CONTINUED) Note 1: When AUDEN = 1, this module functions as if CKE = 0, regardless of its actual value. 2: When FRMEN = 1, SSEN is not used. 3: MCLKEN can only be written when the SPIEN bit = 0. 4: This channel is not meaningful for DSP/PCM mode as LRC follows the FRMSYPW bit. 5: The MCLK source is the REFO clock. |
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