F21 datasheet(226/416 Pages) MICROCHIP

226 / 416 page

PIC24FJ256GA705 FAMILY

DS30010118D-page 226

 2016-2018 Microchip Technology Inc.

I2CxCONH: I2Cx CONTROL REGISTER HIGH

U-0

—

bit 15

bit 8

U-0

R/W-0

—

PCIE

SCIE

BOEN

SDAHT(1)

SBCDE

AHEN

DHEN

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-7

Unimplemented: Read as ‘0’

bit 6

PCIE: Stop Condition Interrupt Enable bit (I2C Slave mode only)

1 = Enables interrupt on detection of Stop condition

0 = Stop detection interrupts are disabled

bit 5

SCIE: Start Condition Interrupt Enable bit (I2C Slave mode only)

1 = Enables interrupt on detection of Start or Restart conditions

0 = Start detection interrupts are disabled

bit 4

BOEN: Buffer Overwrite Enable bit (I2C Slave mode only)

1 = I2CxRCV is updated and an ACK is generated for a received address/data byte, ignoring the state

of the I2COV bit only if RBF bit = 0

0 = I2CxRCV is only updated when I2COV is clear

bit 3

SDAHT: SDAx Hold Time Selection bit(1)

1 = Minimum of 300 ns hold time on SDAx after the falling edge of SCLx

0 = Minimum of 100 ns hold time on SDAx after the falling edge of SCLx

bit 2

SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)

If, on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the

BCL bit is set and the bus goes Idle. This Detection mode is only valid during data and ACK transmit

sequences.

1 = Enables slave bus collision interrupts

0 = Slave bus collision interrupts are disabled

bit 1

AHEN: Address Hold Enable bit (I2C Slave mode only)

1 = Following the 8th falling edge of SCLx for a matching received address byte; SCLREL bit

(I2CxCONL<12>) will be cleared and SCLx will be held low

0 = Address holding is disabled

bit 0

DHEN: Data Hold Enable bit (I2C Slave mode only)

1 = Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the SCLREL

bit (I2CxCONL<12>) and SCLx is held low

0 = Data holding is disabled

Note 1:

This bit must be set to ‘0’ for 1 MHz operation.

F21 数据表(PDF) 226 Page - Microchip Technology

F21 数据表(HTML) 226 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载