F21 datasheet(259/416 Pages) MICROCHIP

259 / 416 page

 2016-2018 Microchip Technology Inc.

DS30010118D-page 259

PIC24FJ256GA705 FAMILY

RTCSTATL: RTCC STATUS REGISTER (LOW)

U-0

—

bit 15

bit 8

U-0

R/C-0

U-0

R/C-0

R-0

—

ALMEVT

—

TSAEVT(1)

SYNC

ALMSYNC

HALFSEC(2)

bit 7

bit 0

Legend:

C = Clearable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-6

Unimplemented: Read as ‘0’

bit 5

ALMEVT: Alarm Event bit

1 = An alarm event has occurred

0 = An alarm event has not occurred

bit 4

Unimplemented: Read as ‘0’

bit 3

TSAEVT: Timestamp A Event bit(1)

1 = A timestamp event has occurred

0 = A timestamp event has not occurred

bit 2

SYNC: Synchronization Status bit

1 = TIME registers may change during software read

0 = TIME registers may be read safely

bit 1

ALMSYNC: Alarm Synchronization Status bit

1 = Alarm registers (ALMTIME and ALMDATE) and Alarm bits (AMASK<3:0>) should not be modified,

and Alarm Control bits (ALRMEN, ALMRPT<7:0>) may change during software read

0 = Alarm registers and Alarm Control bits may be written/modified safely

bit 0

HALFSEC: Half Second Status bit(2)

1 = Second half period of a second

0 = First half period of a second

Note 1:

User software may write a ‘1’ to this location to initiate a Timestamp A event; timestamp capture is not

valid until TSAEVT reads as ‘1’.

This bit is read-only; it is cleared to ‘0’ on a write to the SECONE<3:0> bits.

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