F21 datasheet(272/416 Pages) MICROCHIP

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PIC24FJ256GA705 FAMILY

DS30010118D-page 272

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22.1

User Interface

22.1.1

POLYNOMIAL INTERFACE

The CRC module can be programmed for CRC

polynomials of up to the 32nd order, using up to 32 bits.

Polynomial length, which reflects the highest exponent

in the equation, is selected by the PLEN<4:0> bits

(CRCCON2<4:0>).

The CRCXORL and CRCXORH registers control which

exponent terms are included in the equation. Setting a

particular bit includes that exponent term in the equa-

tion. Functionally, this includes an XOR operation on

the corresponding bit in the CRC engine. Clearing the

bit disables the XOR.

For example, consider two CRC polynomials, one a

16-bit and the other a 32-bit equation.

EQUATION 22-1:

16-BIT, 32-BIT CRC

POLYNOMIALS

To program these polynomials into the CRC generator,

set the register bits, as shown in Table 22-1.

Note that the appropriate positions are set to ‘1’ to indi-

cate that they are used in the equation (for example,

X26 and X23). The ‘0’ bit required by the equation is

always XORed; thus, X0 is a don’t care. For a poly-

nomial of length 32, it is assumed that the 32nd bit will

be used. Therefore, the X<31:1> bits do not have the

32nd bit.

22.1.2

DATA INTERFACE

The module incorporates a FIFO that works with a

variable data width. Input data width can be configured

to any value between 1 and 32 bits using the

DWIDTH<4:0> bits (CRCCON2<12:8>). When the

data width is greater than 15, the FIFO is 4 words deep.

When the DWIDTHx bits are between 15 and 8, the

FIFO is 8 words deep. When the DWIDTHx bits are

less than 8, the FIFO is 16 words deep.

The data for which the CRC is to be calculated must first

be written into the FIFO. Even if the data width is less than

8, the smallest data element that can be written into the

FIFO is 1 byte. For example, if the DWIDTHx bits are 5,

then the size of the data is DWIDTH<4:0> + 1 or 6. The

data is written as a whole byte; the two unused upper bits

are ignored by the module.

Once data is written into the MSb of the CRCDAT reg-

isters (that is, the MSb as defined by the data width),

the value of the VWORD<4:0> bits (CRCCON1<12:8>)

increments by one. For example, if the DWIDTHx bits

are 24, the VWORDx bits will increment when bit 7 of

CRCDATH is written. Therefore, CRCDATL must

always be written to before CRCDATH.

The CRC engine starts shifting data when the CRCGO

bit (CRCCON1<4>) is set and the value of the

VWORDx bits is greater than zero.

Each word is copied out of the FIFO into a buffer

is then shifted out of the buffer. The CRC engine

continues shifting at a rate of two bits per instruction

cycle, until the VWORDx bits reach zero. This means

that for a given data width, it takes half that number of

instructions for each word to complete the calculation.

For example, it takes 16 cycles to calculate the CRC for

a single word of 32-bit data.

When the VWORDx bits reach the maximum value for

the configured value of the DWIDTHx bits (4, 8 or 16),

the CRCFUL bit (CRCCON1<7>) becomes set. When

the VWORDx bits reach zero, the CRCMPT bit

(CRCCON1<6>) becomes set. The FIFO is emptied

and the VWORD<4:0> bits are set to ‘00000’ whenever

CRCEN is ‘0’.

At least one instruction cycle must pass after a write to

CRCWDAT before a read of the VWORDx bits is done.

and

X32+X26 + X23 + X22 + X16 + X12 + X11 + X10 +

X8 + X7 + X5 + X4 + X2 + X + 1

X16 + X12 + X5 + 1

TABLE 22-1:

CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIALS

CRC Control Bits

Bit Values

16-Bit Polynomial

32-Bit Polynomial

PLEN<4:0>

01111

11111

X<31:16>

0000 0000 0000 0001

0000 0100 1100 0001

X<15:1>

0001 0000 0010 000

0001 1101 1011 011

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