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F21 数据表(PDF) 119 Page - Microchip Technology |
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F21 数据表(HTML) 119 Page - Microchip Technology |
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119 / 416 page  2016-2018 Microchip Technology Inc. DS30010118D-page 119 PIC24FJ256GA705 FAMILY REGISTER 10-3: PMD3: PERIPHERAL MODULE DISABLE REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CMPMD RTCCMD PMPMD bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 CRCMD — — — — — I2C2MD — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 CMPMD: Triple Comparator Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 9 RTCCMD: RTCC Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 8 PMPMD: Enhanced Parallel Master Port Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 7 CRCMD: CRC Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 6-2 Unimplemented: Read as ‘0’ bit 1 I2C2MD: I2C2 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 0 Unimplemented: Read as ‘0’ |
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