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F21 数据表(PDF) 162 Page - Microchip Technology |
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F21 数据表(HTML) 162 Page - Microchip Technology |
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162 / 416 page ![]() PIC24FJ256GA705 FAMILY DS30010118D-page 162 2016-2018 Microchip Technology Inc. FIGURE 13-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM TMR3 TMR2 Set T3IF Equal Comparator PR3 PR2 Reset LSB MSB Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.5 “Peripheral Pin Select (PPS)” for more information. 3: The A/D event trigger is available only on Timer2/3 in 32-bit mode and Timer3 in 16-bit mode. Data Bus<15:0> Read TMR2(1) Write TMR2(1) 16 16 16 Q QD CK TGATE 0 1 TCKPS<1:0> 2 A/D Event Trigger(3) T2CK TCY TCS(2) TGATE(2) SOSC Input LPRC Input TECS<1:0> TxCK Gate Sync Prescaler 1, 8, 64, 256 Sync TMR3HLD |
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