AD20B datasheet(68/416 Pages) MICROCHIP

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PIC24FJ256GA705 FAMILY

DS30010118D-page 68

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DMACHn: DMA CHANNEL n CONTROL REGISTER

U-0

r-0

U-0

R/W-0

—

—NULLW

RELOAD(1)

CHREQ(3)

bit 15

bit 8

R/W-0

SAMODE1

SAMODE0

DAMODE1

DAMODE0

TRMODE1

TRMODE0

SIZE

CHEN

bit 7

bit 0

Legend:

r = Reserved bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-13

Unimplemented: Read as ‘0’

bit 12

Reserved: Maintain as ‘0’

bit 11

Unimplemented: Read as ‘0’

bit 10

NULLW: Null Write Mode bit

1 = A dummy write is initiated to DMASRCn for every write to DMADSTn

0 = No dummy write is initiated

bit 9

RELOAD: Address and Count Reload bit(1)

1 = DMASRCn, DMADSTn and DMACNTn registers are reloaded to their previous values upon the

start of the next operation

0 = DMASRCn, DMADSTn and DMACNTn are not reloaded on the start of the next operation(2)

bit 8

CHREQ: DMA Channel Software Request bit(3)

1 = A DMA request is initiated by software; automatically cleared upon completion of a DMA transfer

0 = No DMA request is pending

bit 7-6

SAMODE<1:0>: Source Address Mode Selection bits

11 = DMASRCn is used in Peripheral Indirect Addressing and remains unchanged

10 = DMASRCn is decremented based on the SIZE bit after a transfer completion

01 = DMASRCn is incremented based on the SIZE bit after a transfer completion

00 = DMASRCn remains unchanged after a transfer completion

bit 5-4

DAMODE<1:0>: Destination Address Mode Selection bits

11 = DMADSTn is used in Peripheral Indirect Addressing and remains unchanged

10 = DMADSTn is decremented based on the SIZE bit after a transfer completion

01 = DMADSTn is incremented based on the SIZE bit after a transfer completion

00 = DMADSTn remains unchanged after a transfer completion

bit 3-2

TRMODE<1:0>: Transfer Mode Selection bits

11 = Repeated Continuous mode

10 = Continuous mode

01 = Repeated One-Shot mode

00 = One-Shot mode

bit 1

SIZE: Data Size Selection bit

1 = Byte (8-bit)

0 = Word (16-bit)

bit 0

CHEN: DMA Channel Enable bit

1 = The corresponding channel is enabled

0 = The corresponding channel is disabled

Note 1:

Only the original DMACNTn is required to be stored to recover the original DMASRCn and DMADSTn.

DMASRCn, DMADSTn and DMACNTn are always reloaded in Repeated mode transfers

(DMACHn<2> = 1), regardless of the state of the RELOAD bit.

The number of transfers executed while CHREQ is set depends on the configuration of TRMODE<1:0>.

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