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DS0147 数据表(PDF) 74 Page - Microchip Technology |
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DS0147 数据表(HTML) 74 Page - Microchip Technology |
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74 / 128 page  Unit –1 Max –1 Typ –1 Min STD Max STD Typ STD Min Symbol Parameter Gbps 3.2 0.25 3.2 0.25 FRxRateDC Rx data rate when DC coupled Gbps 1.25 DC 1.25 DC FTXRateOOB Rx OOB (de- serializer bypass) da- ta rate GHz 6.35 1.6 5.1563 1.6 FTXPLL TXPLL out- put frequen- cy 3 Gbps 10.3125 0.25 10.3125 0.25 FRXCDR Rx CDR mode Gbps 12.7 3.0 10.3125 3.0 FRXAUTOCAL Rx DFE and CDR auto- calibration modes 2 Gbps 12.7 3.0 10.3125 3.0 FRXEyeMon Rx Eye Mon- itor mode 2 [Tx|Rx]_CLK Cycles 4 16 16 MPWPCS_RES- ET PCS reset minimum pulse width [Tx|Rx]_CLK Cycles 4 16 16 MPWPMA_RE- SET PMA reset minimum pulse width 1. The reference clock is required to be a minimum of 75 MHz for data rates of 10 Gbps and above. 2. For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05 V mode. See supply tolerance in the section Recommended Operating Conditions. 3. The Tx PLL rate is between 0.5x to 5.5x the Tx data rate. The Tx data rate depends on per XCVR lane Tx post-divider settings. 4. Minimum pulse width should reference TX_CLK when Tx only or both Tx and Rx are used. Reference RX_CLK if only Rx is used. 6.5.2 Transceiver Reference Clock Performance The following table describes performance of the transceiver reference clock. Table 84 • PolarFire SoC Transceiver Reference Clock AC Requirements Unit –1 Max –1 Typ –1 Min STD Max STD Typ STD Min Symbol Parameter MHz 400 20 400 20 FTXREFCLK Reference clock input rate 1, 2 MHz 156 20 156 20 FXCVRREFCLKM- AX CASCADE Reference clock input rate 1, 2, 3 70 Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics |
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