• CSR reads have a three-cycle result latency.

• MUL, MULH, MULHU, and MULHSU have a 5-cycle result latency.

• DIV, DIVU, REM, and REMU have between a 2-cycle and 33-cycle result latency, depending on the operand

values.

The pipeline only interlocks on read-after-write and write-after-write hazards, so instructions may be scheduled to

avoid stalls.

The U54 implements the standard Multiply (M) extension to the RISC-V architecture for integer multiplication and

division. The U54 has a 16-bit per cycle hardware multiply and a 4-bit per cycle hardware divide.

Branch and jump instructions transfer control from the memory access pipeline stage. Correctly predicted branches

and jumps incur no penalty, whereas mispredicted branches and jumps incur a three-cycle penalty.

Most CSR writes result in a pipeline flush with a five-cycle penalty.

3.1.2.5

U54 Data Memory System

The U54 data memory system has a 8-way set-associative 32 KB write-back data cache with 64 B cache lines.

The data cache is Virtually Indexed Physically Tagged (VIPT). Access latency is two clock cycles for words and

double-words, and three clock cycles for smaller quantities. Misaligned accesses are not supported in hardware

and result in a trap to support software emulation. The data caches are kept coherent with a directory-based cache

coherence manager, which resides in the outer L2 cache. Stores are pipelined and commit on cycles where the data

memory system is otherwise idle. Loads to addresses currently in the store pipeline result in a five-cycle penalty.

3.1.2.6

U54 Atomic Operations

The U54 core supports the RISC-V standard Atomic (A) extension on regions of the memory map denoted by the

attribute A. Atomic memory operations to regions that do not support them generate an access exception precisely

at the core. The load-reserved and store-conditional instructions are only supported on cached regions; therefore,

generate an access exception on DTIM and other uncached memory regions. See The RISC-V Instruction Set

Manual, Volume I: User-Level ISA, Version 2.1 [1] for more information on the instructions added by this extension.

3.1.2.7

U54 Floating Point Unit (FPU)

The U54 FPU provides full hardware support for the IEEE

® 754-2008 floating-point standard for 32-bit, single-

precision and 64-bit, double-precision arithmetic. The FPU includes a fully pipelined fused-multiply-add unit and

an iterative divide and square-root unit, magnitude comparators, and float-to-integer conversion units, all with full

hardware support for subnormals and all IEEE default values.

3.1.2.8

U54 Virtual Memory Support

The U54 has support for virtual memory through the use of a Memory Management Unit (MMU). The MMU supports

the Bare and Sv39 modes as described in the RISC-V Instruction Set Manual, Volume II: Privileged Architecture,

Version 1.10 [2]. The U54 MMU has a 39-bit virtual address space mapped to a 38-bit physical address space.

A hardware page-table walker refills the address translation caches. Both instruction and data address translation

caches are fully associative, and have 32 entries. The MMU supports 2 MB megapages and 1 GB gigapages to

reduce translation overheads for large contiguous regions of virtual and physical address space. Note that the U54

does not automatically set the Accessed (A) and Dirty (D) bits in a Sv39 Page Table Entry (PTE). Instead, the U54

MMU will raise a page fault exception for a read to a page with PTE.A=0 or a write to a page with PTE.D=0.

3.1.2.9

U54 Local Interrupts

Each U54 supports up to 48 local interrupt sources that are routed directly to the core. The local interrupts are

sourced from the FPGA fabric. Each U54 core receives the same 48 interrupt sources from the FPGA fabric.

3.1.2.10 U54 Memory Error Correction

The U54 ITIM and DTIM implement single-error correcting, double-error detecting (SECDEC) error correcting code

(ECC). The granularity at which this protection is applied (the codeword) is 32-bit (with an ECC overhead of 7 bits per

codeword).

3.1.2.10.1 U54 Memory Single-Bit Errors

When a single bit error is detected in the U54 L1 memory used as a cache, the error is corrected and the cache

line is flushed consequently writing to the next level in the memory hierarchy (L2 cache). When a single bit error

is detected in the the U54 L1 memory configured as an ITIM, the error is corrected and written back to the ITIM

location.

Microprocessor Subsystem

© 2021 Microchip Technology Inc.

and its subsidiaries

Overview

DS60001656C-page 13