AS7421 datasheet(39/53 Pages) AMSCO

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AS7421

Datasheet

• PUBLIC

DS000667

• v1-00 • 2022-Aug-25

│ 38

10.2.11

CFG_RAM Register (Address 0x6A)

Figure 41:

CFG_RAM Register

Addr: 0x6A

CFG_RAM

Bit

Bit Name

Default

Access

Bit Description

REG_BANK

Select P2RAM

4:0

RAM_OFFSET

Offset address for programming the configuration

into the RAM. Access succeeded via the

addresses CFG_RAM_0 to CFG_RAM_31.

0x0C: SMUX for integration cycle A

0x0D: SMUX for integration cycle B

0x0E: SMUX for integration cycle C

0x0F: SMUX for integration cycle D

0x10: ASETUP for integration cycle A/B

0x11: ASETUP for integration cycle C/D

0x12: COMPDAC for modulators and integrators

Others: Reserved

10.2.12

CFG_GPIO Register (Address 0x6B)

Figure 42:

CFG_GPIO Register

Addr: 0x6B

CFG_GPIO

Bit

Bit Name

Default

Access

Bit Description

GPIO_INVERT

GPIO invert

0: Input/output not inverted

1: Input/output inverted

GPIO_OEN

GPIO output enable

0: GPIO output disabled

1: GPIO output enabled

GPIO_OUT

GPIO output

GPIO_IN

GPIO input

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