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STM32F103XC 数据表(PDF) 13 Page - STMicroelectronics |
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STM32F103XC 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 143 page ![]() DS5792 Rev 13 13/143 STM32F103xC, STM32F103xD, STM32F103xE Description 135 Figure 2. Clock tree 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz. 2. For the USB function to be available, both HSE and PLL must be enabled, with the USBCLK at 48 MHz. 3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz. |
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