STM32F103ZCT7XXX datasheet(107/143 Pages) STMICROELECTRONICS

107 / 143 page

DS5792 Rev 13

107/143

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

135

Equation 1: RAIN max formula

The formula above (Equation 1) is used to determine the maximum external impedance

allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

Guaranteed by characterization results.

2. Guaranteed by design.

3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.

Refer to Section 3: Pinouts and pin descriptions for further details.

4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 59.

Table 60. RAIN max for fADC = 14 MHz(1)

1. Guaranteed by design.

Ts (cycles)

tS (µs)

RAIN max (kΩ)

1.5

0.11

0.4

7.5

0.54

5.9

13.5

0.96

11.4

28.5

2.04

25.2

41.5

2.96

37.2

55.5

3.96

71.5

5.11

239.5

17.1

Table 61. ADC accuracy - limited test conditions(1)(2)

1. ADC DC accuracy values are measured after internal calibration.

2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any analog input pins should

be avoided as this significantly reduces the accuracy of the conversion being performed on another analog

input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially

inject negative current.

Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.14 does not

affect the ADC accuracy.

Symbol

Parameter

Test conditions

Typ

Max(3)

3. Guaranteed by characterization results.

Unit

Total unadjusted error

fPCLK2 = 56 MHz,

fADC = 14 MHz, RAIN < 10 kΩ,

VDDA = 3 V to 3.6 V

TA = 25 °C

Measurements made after

ADC calibration

VREF+ = VDDA

±1.3

±2

LSB

Offset error

±1

±1.5

Gain error

±0.5

±1.5

Differential linearity error

±0.7

±1

Integral linearity error

±0.8

±1.5

AIN

ADC

()

----------------------------------------------------------------

ADC

–

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