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CC2430-RTR1-F128 数据表(PDF) 56 Page - Texas Instruments |
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CC2430-RTR1-F128 数据表(HTML) 56 Page - Texas Instruments |
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56 / 234 page  CC2430 CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A Page 56 of 232 IEN2 (0x9A) – Interrupt Enable 2 Bit Name Reset R/W Description 7:6 - 00 R0 Not used. Read as 0 WDTIE – Watchdog timer interrupt enable 0 Interrupt disabled 5 WDTIE 0 R/W 1 Interrupt enabled P1IE– Port 1 interrupt enable 0 Interrupt disabled 4 P1IE 0 R/W 1 Interrupt enabled UTX1IE – USART1 TX interrupt enable 0 Interrupt disabled 3 UTX1IE 0 R/W 1 Interrupt enabled UTX0IE - USART0 TX interrupt enable 0 Interrupt disabled 2 UTX0IE 0 R/W 1 Interrupt enabled P2IE – Port 2 interrupt enable 0 Interrupt disabled 1 P2IE 0 R/W 1 Interrupt enabled RFIE – RF general interrupt enable 0 Interrupt disabled 0 RFIE 0 R/W 1 Interrupt enabled 12.7.2 Interrupt Processing When an interrupt occurs, the CPU will vector to the interrupt vector address as shown in Table 29. Once an interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a RETI (return from interrupt instruction). When an RETI is performed, the CPU will return to the instruction that would have been next when the interrupt occurred. When the interrupt condition occurs, the CPU will also indicate this by setting an interrupt flag bit in the interrupt flag registers. This bit is set regardless of whether the interrupt is enabled or disabled. If the interrupt is enabled when an interrupt flag is set, then on the next instruction cycle the interrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector address. Interrupt response will require a varying amount of time depending on the state of the CPU when the interrupt occurs. If the CPU is performing an interrupt service with equal or greater priority, the new interrupt will be pending until it becomes the interrupt with highest priority. In other cases, the response time depends on current instruction. The fastest possible response to an interrupt is seven machine cycles. This includes one machine cycle for detecting the interrupt and six cycles to perform the LCALL. |
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