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CC2430-RTR1-F32Z 数据表(PDF) 71 Page - Texas Instruments |
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CC2430-RTR1-F32Z 数据表(HTML) 71 Page - Texas Instruments |
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71 / 234 page  CC2430 CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A Page 71 of 232 Table 36: Peripheral I/O Pin Mapping P0 P1 P2 Periphery / Function 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 4 3 2 1 0 ADC A7 A6 A5 A4 A3 A2 A1 A0 C SS M0 MI USART0 SPI Alt. 2 M O MI C SS RT CT TX RX USART0 UART Alt. 2 TX RX RT CT MI M0 C SS USART1 SPI Alt. 2 MI M0 C SS RX TX RT CT USART1 UART Alt. 2 RX TX RT CT 2 1 0 TIMER1 Alt. 2 0 1 2 1 0 TIMER3 Alt. 2 1 0 1 0 TIMER4 Alt. 2 1 0 32.768 kHz XOSC Q2 Q1 DEBUG D C D D 13.1.4.1 USART0 The SFR register bit PERCFG.U0CFG selects whether to use alternative 1 or alternative 2 locations. In Table 36, the USART0 signals are shown as follows: UART: • RX : RXDATA • TX : TXDATA • RT : RTS • CT : CTS SPI: • MI : MISO • MO : MOSI • C : SCK • SS : SSN P2DIR.PRIP0 selects the order of precedence when assigning several peripherals to port 0. When set to 00, USART0 has precedence. Note that if UART mode is selected and hardware flow control is disabled, USART1 or timer 1 will have precedence to use ports P0_4 and P0_5. P2SEL.PRI3P1 and P2SEL.PRI0P1 select the order of precedence when assigning several peripherals to port 1. USART0 has precedence when both are set to 0. Note that if UART mode is selected and hardware flow control is disabled, timer 1 or timer 3 will have precedence to use ports P1_2 and P1_3. 13.1.4.2 USART1 The SFR register bit PERCFG.S1CFG selects whether to use alternative 1 or alternative 2 locations. In Table 36, the USART1 signals are shown as follows: • RX : RXDATA • TX : TXDATA |
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