5

A/D, D/C Converters for Image Signal Processing

MN65543S

Timing Chart

The chip samples the analog input at the falling edge of the clock signal and provides the corresponding digital

output 2.5 clock cycles later at the rising edge of the clock signal.

Clock

Analog input

Data output

N

N+1

N–3

N–2

N–1

N+1

N

N+2

N+3

N+4

Note: The circles indicate analog signal sampling points.