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HT95L00P 数据表(PDF) 21 Page - Holtek Semiconductor Inc |
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HT95L00P 数据表(HTML) 21 Page - Holtek Semiconductor Inc |
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21 / 51 page  HT95CXXX Rev. 1.50 21 May 26, 2005 Reading TMR0H latches the TMR0L into the low byte buffer to avoid a false timing problem. Reading TMR0L returns the contents of the low byte buffer. In other words, the low byte of the Timer/Event Counter 0 can not be read directly. It must read the TMR0H first to make the low byte contents of Timer/Event Counter 0 be latched into the buffer. There are 3 registers related to the Timer/Event Counter 1; TMR1H, TMR1L and TMR1C. The Timer/Event Counter 1 operates in the same manner as the Timer/Event Counter 0. The TMR0C is the Timer/Event Counter 0 control regis- ter, which defines the Timer/Event Counter 0 options. The Timer/Event Counter 1 has the same options as the Timer/Event Counter 0 and is defined by TMR1C. The timer/event counter control registers define the operat- ing mode, counting enable or disable and active edge. The T0M0/T1M0, T0M1/T1M1 bits define the operating mode. The event count mode is used to count external events, which means the clock source comes from an external (TMR0 or INT/TMR1) pin. The timer mode func- tions as a normal timer with the clock source coming from instruction clock (TMR0) or 32768Hz (TMR1). The pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR0 or INT/TMR1). The counting is based on the 32768Hz clock for TMR1 or instruction clock for TMR0. T 0 M 1 / T 1 M 1 T 0 M 0 / T 1 M 0 I N T / T M R 1 T M R 0 T 0 E / T 1 E P u l s e W i d t h M e a s u r e m e n t M o d e C o n t r o l T i m e r / E v e n t C o u n t e r 0 / 1 P r e l o a d R e g i s t e r T i m e r / e v e n t C o u n t e r 0 / 1 D a t a B u s R e l o a d O v e r f l o w t o I n t e r r u p t T i m e r 0 : I n s t r u c t i o n c l o c k ( s y s t e m c l o c k / 4 ) T i m e r 1 : 3 2 7 6 8 H z L o w B y t e B u f f e r T 0 M 1 / T 1 M 1 T 0 M 0 / T 1 M 0 T 0 O N / T 1 O N Timer/Event Counter 0/1 Bit No. Label R/W Function 0~2 ¾ RO Unused bit, read as ²0² 3 T0E/T1E RW To define the TMR0/TMR1 active edge of timer For event count or Timer mode (0=active on low to high; 1=active on high to low) For pulse width measurement mode (0=measures low pulse width; 1=measures high pulse width) 4 T0ON/T1ON RW To enable/disable timer counting (0=disabled; 1=enabled) 5 ¾ RO Unused bit, read as ²0² 6 7 T0M0/T1M0 T0M1/T1M1 RW To define the operating mode Bit 7, 6=01, Event count mode (external clock) Bit 7, 6=10, Timer mode Bit 7, 6=11, Pulse width measurement mode Bit 7, 6=00, Unused TMR0C (0EH)/TMR1C (11H) Register Register Bit No. R/W Function TMR0H (0CH) 0~7 RW Timer/Event Counter 0 higher-order byte register TMR0L (0DH) 0~7 RW Timer/Event Counter 0 lower-order byte register TMR1H (0FH) 0~7 RW Timer/Event Counter 1 higher-order byte register TMR1L (10H) 0~7 RW Timer/Event Counter 1 lower-order byte register |
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