ICS570

MDS 570 I

1

Revision 030905

Integrated Circuit Systems, Inc.

Multiplier and Zero Delay Buffer

Description

The ICS570 is a high-performance Zero Delay Buffer

(ZDB) which integrates ICS’ proprietary analog/digital

Phase Locked Loop (PLL) techniques. The A version is

recommended for 5 V designs and the B version for

family, and was designed as a performance upgrade to

meet today’s higher speed and lower voltage

requirements. The zero delay feature means that the

rising edge of the input clock aligns with the rising

edges of both output clocks, giving the appearance of

no delay through the device. There are two outputs on

the chip, one being a low-skew divide by two of the

other output. The device incorporates an all-chip power

down/tri-state mode that stops the internal PLL and

puts both outputs into a high impedance state.

The ICS570 is ideal for synchronizing outputs in a large

variety of systems, from personal computers to data

communications to graphics/video. By allowing off-chip

feedback paths, the device can eliminate the delay

through other devices.

The ICS570 A and B versions were designed to

improve input to output jitter from the original ICS570M

version, and are recommended for all new designs.

Features

only)

replacement)

outputs)

from 0.5x to 32x

at TTL levels

Block Diagram

Ph as e

Detec tor,

C harge

Pum p,

and Loop

F ilter

divide

by N

CL K

E xte rn al fe ed ba ck ca n c o m e from C L K or C L K /2 (s ee ta b le on pa ge 2 )

IC L K

FBIN

S1 :0

VC O

CL K 2

/2