Multiplier and Zero Delay Buffer

MDS 570 I

5

Revision 030905

Integrated Circuit Systems, Inc.

ICS570

Clock Period Jitter Tables (ICS570B)

All jitter values are considered typical measured at 25

°C with 27Ω termination resistor and 15 pF loads on

both CLK and CLK/2. The feedback is from CLK/2 to FBIN. Note that if an output is unused, it should be left

unconnected to improve output jitter on the active output clocks.

Absolute and One Sigma Jitter (ps)

Absolute and One Sigma Jitter (ps)

Absolute and One Sigma Jitter (ps)

CLK = 50M

CLK/2 = 25M

S1

S0

CLKIN (MHz)

Multiplier

P to P

1 sigma

Multiplier

P to P

1 sigma

0

M

8.333

6x

±110

80

3x

±55

20

0

1

6.25

8x

±125

90

4x

±50

20

M

0

3.125

16x

±130

90

8x

±55

20

M

M

4.167

12x

±120

90

6x

±55

20

M

1

2.5

20x

±115

90

10x

±55

20

1

0

25

2x

±130

50

1x

±55

20

1

M

1.5625

32x

±120

90

16x

±55

20

1

1

12.5

4x

±120

60

2x

±55

20

CLK = 100M

CLK/2 = 50M

S1

S0

CLKIN (MHz)

Multiplier

P to P

1 sigma

Multiplier

P to P

1 sigma

0

M

16.667

6x

±100

70

3x

±45

20

0

1

12.5

8x

±100

70

4x

±45

20

M

0

6.25

16x

±110

80

8x

±45

20

M

M

8.333

12x

±100

70

6x

±45

20

M

1

5

20x

±105

70

10x

±40

20

1

0

50

2x

±90

60

1x

±40

20

1

M

3.125

32x

±95

70

16x

±45

20

1

1

25

4x

±105

70

2x

±60

20

CLK = 150M

CLK/2 = 75M

S1

S0

CLKIN (MHz)

Multiplier

P to P

1 sigma

Multiplier

P to P

1 sigma

0

M

25

6x

±115

70

3x

±50

20

0

1

18.375

8x

±120

80

4x

±50

20

M

0

9.375

16x

±130

90

8x

±50

20

M

M

12.5

12x

±130

90

6x

±45

20

M

1

7.5

20x

±130

90

10x

±45

20

1

0

75

2x

±115

90

1x

±45

20

1

M

4.6875

32x

±130

90

16x

±50

20

1

1

37.5

4x

±110

70

2x

±60

20