7

Layout

7.1

Layout guidelines and considerations

Inorder to optimize the PCB layout, following considerations should be taken into account:

•

SMT ceramic capacitors (or different types of low-ESR and low-ESL capacitors) must be placed close to

each supply rail pins. A 100 nF capacitor must be placed between VDD and GND and between VH and

GNDISO, as close as possible to device pins, in order to filter high-frequency noise and spikes. In order to

provide local storage for pulsed current a second capacitor with value in the range between 1 µF and 10 µF

should also be placed close to the supply pins.

•

As a good practice it is suggested to add filtering capacitors close to logic inputs of the device (IN+, IN-), in

particular for fast switching or noisy applications.

•

The power transistors must be placed as close as possible to the gate driver, so to minimize the gate loop

area and inductance that might bring to noise or ringing.

•

To avoid degradation of the isolation between the primary and secondary side of the driver, there should not

be any trace or conductive area below the driver.

•

If the system has multiple layers, it is recommended to connect the VH and GNDISO pins to internal ground

or power planes through multiple vias of adequate size. These vias should be located close to the IC pins to

maximize thermal conductivity.

7.2

Layout example

Anexample of STGAP2SC Half-Bridge PCB layout with main signals highlighted by different colors is shown in

Figure 11 . It is recommended to follow this example for proper positioning and connection of filtering capacitors.

Q1

Q2

U1

U2

G1

D1

S1

G2

D2

S2

TOP

BOTTOM

STGAP2S

Layout

DS12541 - Rev 3

page 13/23