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WM8786GEDS/V 数据表(PDF) 16 Page - Wolfson Microelectronics plc

部件名 WM8786GEDS/V
功能描述  24-Bit, 192kHz Stereo ADC
PDF  22 Pages
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制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM8786GEDS/V 数据表(HTML) 16 Page - Wolfson Microelectronics plc

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WM8786
Pre-Production
w
PP Rev 3.0 December 2005
16
Figure 15a Master Mode
Figure 15b Slave Mode
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
Figure 16 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before an LRCLK
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.
Figure 17 Right Justified Audio Interface (assuming n-bit word length)



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