Also, some designs use an input resistor on the positive input, generally of the same value than the input

resistance on the negative input. This resistor can be useful to balance the input currents on the positive and

negative inputs, and reduce the impact of those input currents on precision. However, this is not useful on the

TSV772 as the input currents are very low. Furthermore, this resistor can also interact with the input capacitances

to generate a pole. The frequency of this pole should be kept higher than the closed-loop bandwidth frequency.

The macromodel provided takes into account the circuit parasitic capacitors. Thus, a transient SPICE simulation

(100 mV step) is an easy way to evaluate the stability of the application. However, this cannot replace a hardware

evaluation of the application circuit.

5.8

Settling time

Settling time in an application can be defined as the amount of time between the input changes, and the output

reaching its final value. It is usually defined with a given tolerance, so the output stability is reached when

the output stays within the given range around the final value. In Figure 30 and Figure 31, the settling time is

measured in an inverting configuration, using the so-called “false summing node” circuit.

Figure 47. Settling time measurement configuration

This circuit is used with a step input voltage from a positive or negative value, to 0 V. The measurement point

being (Vin + Vout) / 2, and Vout being in an ideal circuit equal to Vin; the measurement point gives half of the

error on Vout, comparatively to Vin. This error is compared to the tolerance, 0.1% for this circuit, to deduce the

settling time. This characteristic is particularly useful when driving an ADC. It is related to the slew rate, GBP and

stability of the circuit. It also varies with the circuit gain, the circuit load, and the input voltage step value. However,

computing the value of the settling time in a given configuration is not straightforward. The macromodel can give a

good estimation, but prototyping can be needed for fine circuit optimization.

5.9

PCB layout recommendations

Particular attention must be paid to the layout of the PCB tracks connected to the amplifier, load, and power

supply. The power and ground traces are critical as they must provide adequate energy and grounding for

all circuits. The best practice is to use short and wide PCB traces to minimize voltage drops and parasitic

inductance. In addition, to minimizing parasitic impedance over the entire surface, a multi-via technique that

connects the bottom and top layer ground planes together in many locations is often used. The copper traces that

connect the output pins to the load and supply pins should be as wide as possible to minimize trace resistance.

5.10

Decoupling capacitor

In order to ensure op amp full functionality, it is mandatory to place a decoupling capacitor of at least 22 nF as

close as possible to the op amp supply pins. A good decoupling helps to reduce electromagnetic interference

impact.

TSV771, TSV772

Settling time

DS13842 - Rev 3

page 21/32