Description

L5964

6/16

DB4679 Rev 1

Figure 1. Simplified, general block diagram

2 A/3.5 A*

Synchronization 125 kHz to 2.3 MHz

Free running 270 kHz or 2.2 MHz

BUCK1

TESTMODE

WAKEL

WDI

MODE

TJTEST

FDIVISION

SYNCIN

FREQSET

PGDELAYLDO

PGTHLDO

ENLDO

VINLDO

OCPSET2

PGTH2

PGDELAY2

ENBUCK2

PGND2

VINBUCK2

OCPSET1

PGTH1

PGDELAY1

ENBUCK1

PGND1

VINBUCK1

IGN_BUF

HSD_EN

UV/OV x

RESET

SYNCOUT

PGLDO

FBLDO

VOUTLDO

PGOV2

COMP2

FB2

PHASE2

BS2

PGOV1

COMP1

FB1

PHASE1

BS1

BUCK2

Free running 270 kHz or 2.2 MHz

Synchronization 125 kHz to 2.3 MHz

2 A/3.5 A*

250mA

LDO

LOGIC CORE

supervisor

Voltage

Frequency manager

Window watchdog

Reset

VBAT

SWGND

AGND

GADG2411171534PS

* > 2 A operation requires the addition of external Schottky diodes