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L9908 数据表(PDF) 24 Page - STMicroelectronics |
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L9908 数据表(HTML) 24 Page - STMicroelectronics |
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24 / 153 page  5.2 Internal resets (INT_RST, CFG_RST) L9908 implements two different reset states following two different reset signals INT_RST and CFG_RST. • INT_RST (active LOW) is the main internal reset signal; when active it resets the whole logic system. This signal is generated via the reset logic by supervising Internal Supply Monitor, VDD Monitor and ICM outputs: if a fault is verified the internal reset is activated. The internal INT_RST can be alternatively triggered through an activation key written into a dedicated SPI register SW_RESET_KEY. Table 13. SW reset activation register SW_RESET_KEY <7:0> Description 0xCC SW Reset Activation • CFG_RST (active LOW) is the reset signal configuration register. This signal is generated via the reset logic by supervising the NDIS pin status level: if a ‘0’ logic level is detected for a time interval greater than T_ndis_flt the reset is activated. Table 14. Internal resets sources and filtering Condition Action Filter timer for Reset NDIS=’0’ CFG_RST=0 T_ndis_flt UV on V3V3_ANA CFG_RST=0 INT_RST=0 T_por_ltoh_flt UV on V3V3_DIG CFG_RST=0 INT_RST=0 T_por_ltoh_flt OV on V3V3_ANA CFG_RST=0 INT_RST=0 T_por_ltoh_flt OV on V3V3_DIG CFG_RST=0 INT_RST=0 T_por_ltoh_flt UV on BG MAIN CFG_RST=0 INT_RST=0 T_por_ltoh_flt UV on BG AUXILIARY CFG_RST=0 INT_RST=0 T_por_ltoh_flt UV on VDD CFG_RST=0 INT_RST=0 T_por_ltoh_flt CLK1 timeout (stuck) CFG_RST=0 INT_RST=0 ICM Timeout SW Reset SPI frame CFG_RST=0 INT_RST=0 NA L9908 Internal resets (INT_RST, CFG_RST) DS13546 - Rev 3 page 24/153 |
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