L99VR01STR datasheet(45/47 Pages) STMICROELECTRONICS

45 / 47 page

List of figures

Figure 1.

Functional block diagram of L99VR01S ................................................... 3

Figure 2.

Functional block diagram of L99VR01J ................................................... 4

Figure 3.

Pins configuration .................................................................. 5

Figure 4.

Output voltage vs Tj ............................................................... 13

Figure 5.

Output voltage vs VS .............................................................. 13

Figure 6.

Drop voltage vs output current ........................................................ 13

Figure 7.

Current consumption vs output current .................................................. 13

Figure 8.

Current consumption vs input voltage (Io < 1mA) ........................................... 13

Figure 9.

Current consumption vs input voltage (Io = 50 mA) .......................................... 13

Figure 10.

Current consumption vs input voltage (Io= 100 mA) ......................................... 14

Figure 11.

Short-circuit current vs Tj (Ishort pin floating) .............................................. 14

Figure 12.

Short-circuit current vs Tj (Ishort pin tied to GND) ........................................... 14

Figure 13.

Short-circuit current vs input voltage .................................................... 14

Figure 14.

Output voltage vs enable voltage (VO =0.8 V) ............................................. 14

Figure 15.

Output voltage vs enable voltage (VO =1.2 V) ............................................. 14

Figure 16.

Output voltage vs enable voltage (VO =1.5 V) .............................................. 15

Figure 17.

Output voltage vs enable voltage (VO =1.8 V) ............................................. 15

Figure 18.

Output voltage vs enable voltage (VO =2.5 V) ............................................. 15

Figure 19.

Output voltage vs enable voltage (VO =2.8 V) .............................................. 15

Figure 20.

Output voltage vs enable voltage (VO =3.3 V) ............................................. 15

Figure 21.

Output voltage vs enable voltage (VO =5 V) ............................................... 15

Figure 22.

VEn_high vs Tj .................................................................. 15

Figure 23.

VEn_low vs Tj ................................................................... 15

Figure 24.

Vwhth vs Tj ..................................................................... 16

Figure 25.

Vwlth vs Tj ...................................................................... 16

Figure 26.

Icwc vs Tj....................................................................... 16

Figure 27.

Icwd vs Tj ...................................................................... 16

Figure 28.

PSRR ......................................................................... 16

Figure 29.

Load regulation test circuit ........................................................... 17

Figure 30.

Maximum load variation response ..................................................... 17

Figure 31.

Application schematic .............................................................. 18

Figure 32.

Application schematic – Post regulation .................................................. 18

Figure 33.

Behavior of output current versus regulated voltage Vo ....................................... 19

Figure 34.

Ishort versus Rsh ................................................................. 20

Figure 35.

Example of output voltage selection .................................................... 21

Figure 36.

Typical example of enable control ...................................................... 21

Figure 37.

Reset timing diagram............................................................... 22

Figure 38.

Watchdog timing diagram............................................................ 23

Figure 39.

Thermal warning diagram............................................................ 24

Figure 40.

Square wave on TW pin generated during an overvoltage ..................................... 24

Figure 41.

Warning signal caused by overvoltage and thermal warning on TW pin ............................ 25

Figure 42.

Undervoltage lockout on output voltage .................................................. 26

Figure 43.

Typical application................................................................. 28

Figure 44.

PowerSSO-12 PC board ............................................................ 29

Figure 45.

Rthj-amb vs PCB copper area in open box free air condition (PowerSSO-12) ........................ 30

Figure 46.

PowerSSO-12 thermal impedance junction ambient single pulse................................. 30

Figure 47.

Thermal fitting model of a Vreg in PowerSSO-12 ........................................... 31

Figure 48.

SO-8 PC board................................................................... 32

Figure 49.

Rthj-amb vs PCB copper area in open box free air condition.................................... 33

Figure 50.

SO-8 thermal impedance junction ambient single pulse ....................................... 33

Figure 51.

Thermal fitting model of a Vreg in SO-8 .................................................. 34

L99VR01

List of figures

DS13649 - Rev 3

page 45/47

L99VR01STR 数据表(PDF) 45 Page - STMicroelectronics

L99VR01STR 数据表(HTML) 45 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

数据表下载