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COM90C66 数据表(PDF) 73 Page - SMSC Corporation

部件名 COM90C66
功能描述  ARCNET Controller/Transceiver with AT Interface and On-Chip RAM
PDF  76 Pages
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制造商  SMSC [SMSC Corporation]
网页  http://www.smsc.com
标志 SMSC - SMSC Corporation

COM90C66 数据表(HTML) 73 Page - SMSC Corporation

Back Button COM90C66 Datasheet HTML 68Page - SMSC Corporation COM90C66 Datasheet HTML 69Page - SMSC Corporation COM90C66 Datasheet HTML 70Page - SMSC Corporation COM90C66 Datasheet HTML 71Page - SMSC Corporation COM90C66 Datasheet HTML 72Page - SMSC Corporation COM90C66 Datasheet HTML 73Page - SMSC Corporation COM90C66 Datasheet HTML 74Page - SMSC Corporation COM90C66 Datasheet HTML 75Page - SMSC Corporation COM90C66 Datasheet HTML 76Page - SMSC Corporation  
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73
FIGURE 17 - READ I/O CYCLE
Parameter
min
typ
max
units
t1
t2
t3
t4
t5
t6
t7
t8
t9
Address, nSBHE Set Up to BALE Low *
Address, nSBHE Hold after BALE Low *
Address, nSBHE, AEN Set Up to nIOR Low
nIOR Low to Valid Data
nIOR Low to nTOPH, nTOPL Low
A2-A15 Valid, AEN Low to nIOCS16 Low
nIOR High to nTOPH, nTOPL High
nIOR High to Data High Impedance
nIOR High to BALE High (Next Address)
20
20
25
0
0
0
0
30
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
80
30
25
15
20
For latched addresses, t1 and t2 do not apply. Please refer to Figure 21 for Latched Address
Mode.
130 nS minimum inactive time on consecutive reads from Data Register of the COM90C66.
Modified Version of Page 52 for Rev. D COM90C66 Only.
*
**
VALID
AEN
A0-A15,
BALE
nIOR
D0-D7
nTOPL
t1
t2
t3
t4
t5
t7
t8
t9
nSBHE
D0-D15
nTOPH,
nIOCS16
t6
or
VALID DATA
**
t10
t10
AEN Hold after nIOR High
10
nS



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